https://www.linkinstruments.com/wiki/index.php?action=history&feed=atom&title=MSO28_Registers 2026-04-19T09:45:36Z Revision history for this page on the wiki MediaWiki 1.35.9 https://www.linkinstruments.com/wiki/index.php?title=MSO28_Registers&diff=12&oldid=prev 2021-01-16T12:45:58Z

<p>Created page with &quot;==MSO-28 control registers== ==Serial port setup== Simulated Serial port, Virtual Com port -&gt; USB -&gt; Parallel FPGA Baud Rate 460800, 8N1 Buffer threshold 3072 ==Attention k...&quot;</p> <p><b>New page</b></p><div>==MSO-28 control registers==<br /> <br /> ==Serial port setup==<br /> Simulated Serial port, Virtual Com port -&gt; USB -&gt; Parallel FPGA<br /> Baud Rate 460800, 8N1 <br /> Buffer threshold 3072<br /> <br /> ==Attention keyword==<br /> @LDS~<br /> <br /> ==Register to ASCII translation==<br /> Todo<br /> <br /> ==Power On test code==<br /> @LDS~^PNP~<br /> ==Power Off test code==<br /> @LDS~N@~<br /> <br /> ==DSO, LA control registers==<br /> ==0x00==<br /> <br /> ==0x01 R== <br /> Buffer Data 1024 x 4 words<br /> every four byte reads = 1 position :10 bits(DSO) x 2 + 8 LA bits + 1 USB bit + 3 dummy bits <br /> <br /> ==0x02 R== <br /> TrigStat (0..3)<br /> 0000 - DSO reset<br /> 0001 - Waiting for Arming<br /> 0010 - Armed <br /> 0011 - Filling Pretrigger buffer<br /> 0100 - Filling complete waiting for Trigger event to happen<br /> 0101 - Trigger happened, filling post trigger buffer<br /> 0110 - Capture complete, waiting for data read command<br /> 0111 - Reading Buffer<br /> 1000 - Waiting for End of read buffer<br /> 4 - PwrDn reg readback<br /> 5 - SDO_ADC<br /> 6 - SDO_Mem <br /> 7 - not use<br /> <br /> ==0x03 W==<br /> 0..7 - DSO TrigVal(0..7) LSB <br /> ==0x04 W== <br /> 0,1 - DSO TrigVal(8,9)<br /> 2 - MagTrigSlp 1= True/Rising, 0 = False/Falling<br /> 3, 4 - TrigValSel<br /> 00 - Ch 0<br /> 01 - Ch 1<br /> 5,6 - TrigModeSel<br /> 00 - DSO Magnitude Trig<br /> 01 - DSO Width Trig Less Than<br /> 10 - DSO Width Trig Greater or Equal<br /> 11 - Not used<br /> 7 - not used<br /> <br /> ==0x05 W==<br /> 0,2 - TrigChSelVal<br /> 000 - ChA<br /> 001 - ChB<br /> 010 - Logic<br /> 011 - nc<br /> 100 - SPI<br /> 101 - I2C<br /> 110 - nc<br /> 111 - nc<br /> <br /> 3 - LogTrigSlp<br /> 4 - DC Relay Ch0, 0 = AC, 1 = DC<br /> 5 - DC Relay Ch1, 0 = AC, 1 = DC<br /> 6 - Attn Ch0, 0 = /10, 1 = /1<br /> 7 - Attn Ch1, 0 = /10, 1 = /1<br /> <br /> ==0x06 W==<br /> 0 - SCLK<br /> 1 - SDIO<br /> 2 - CSB (active H)<br /> 3 - CSDAC1 (active H)<br /> 4 - CSDAC2 (active H)<br /> 5 - CSMem (active H)<br /> 6,7 - Not Used<br /> <br /> ==0x07 W==<br /> 0..7 - TrigPos(0..7)<br /> <br /> ==0x08 W==<br /> 0..7 - TrigPos(8,15)<br /> <br /> ==0x09 W== <br /> 0,1 - Clk source select 00=50Mhz, 01=100Mhz, 10=200Mhz, 11= 20Mhz and below<br /> 2,7 - ClkDiv bit 8,13<br /> <br /> ==0x0A W==<br /> 0..7 - ClkDiv bit 0..7 (Clk rate = 100 Mhz / (ClkDiv-1)<br /> <br /> ==0x0B W==<br /> 0..7 - TrigWidthVal(0..7)<br /> <br /> ==0x0C W==<br /> 0..7 - Logic Tirgger Val<br /> <br /> ==0x0D W==<br /> 0..7 - Logic don't Care, 1 marks the bit position of don't care bit <br /> <br /> ==0x0E W== <br /> 0 - FSMReset 1= resets DSO FSM (pulse on write to reg) <br /> 1 - Armed DSO 1= Arms DSO for capture (pulse on write to reg) <br /> 2 - ReadMode 1= Buffer Read Back, 0= DSO <br /> 3 - TrigEnd 1= Forces a fake trig (pulse on write to reg) <br /> 4 - PwrDn 1= power down default = 0 <br /> 5 - not use<br /> 6 - ADCRst 1= Reset ADC default = 0 needs software pulse <br /> 7 - not use<br /> <br /> ==0x0F W== <br /> *0 - Alternate Address Page 1<br /> *1 - Alternate Address Page 2<br /> 2 - not used<br /> 3 - not used<br /> 4 - TrigOutSel, 1 = Cal 1khz out 0 = TrigPulseOut, Default = Off<br /> 5 - SlwClkMode, 1 = On, 0 = Off, Default = Off<br /> 6 - Glitch Trigger, 1 = On, 0 = Off, Default = Off<br /> 7 - Auto Trigdone reply control, Default = off <br /> <br /> ==Serial Trigger Registers==<br /> *Alt_2 0x00 Serial TrigWd (31 downto 24) first bits to enter the shift register<br /> *Alt_2 0x01 Serial TrigWd (23 downto 16)<br /> *Alt_2 0x02 Serial TrigWd (15 downto 8)<br /> *Alt_2 0x03 Serial TrigWd (7 downto 0) last bits to enter the shift register<br /> *Alt_2 0x04 Serial TrigWd Ignor(31 downto 24)<br /> *Alt_2 0x05 Serial TrigWd Ignor(23 downto 16)<br /> *Alt_2 0x06 Serial TrigWd Ignor(15 downto 8)<br /> *Alt_2 0x07 Serial TrigWd Ignor(7 downto 0)<br /> *Alt_2 0x08 0,1 - SPI Mode<br /> 00 - Mode 0<br /> 01 - Mode 1<br /> 10 - Mode 2<br /> 11 - Mode 3<br /> 2 - SPI Trigdata Source, 0 = SI, 1 = SO, default = SI<br /> 3..7 - Not used</div>

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