MSO28 Registers

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MSO-28 control registers

Serial port setup

Simulated Serial port, Virtual Com port -> USB -> Parallel FPGA Baud Rate 460800, 8N1 Buffer threshold 3072

Attention keyword

@LDS~

Register to ASCII translation

Todo

Power On test code

@LDS~^PNP~

Power Off test code

@LDS~N@~

DSO, LA control registers

0x00

0x01 R

Buffer Data 1024 x 4 words
every four byte reads = 1 position :10 bits(DSO) x 2 + 8 LA bits + 1 USB bit + 3 dummy bits 

0x02 R

TrigStat (0..3)
0000 - DSO reset
0001 - Waiting for Arming
0010 - Armed 
0011 - Filling Pretrigger buffer
0100 - Filling complete waiting for Trigger event to happen
0101 - Trigger happened, filling post trigger buffer
0110 - Capture complete, waiting for data read command
0111 - Reading Buffer
1000 - Waiting for End of read buffer
4 - PwrDn reg readback
5 - SDO_ADC
6 - SDO_Mem	
7 - not use

0x03 W

0..7 - DSO TrigVal(0..7) LSB	

0x04 W

0,1 - DSO TrigVal(8,9)
2 - MagTrigSlp 1= True/Rising, 0 = False/Falling
3, 4 - TrigValSel

00 - Ch 0

	01 - Ch 1
5,6 - TrigModeSel

00 - DSO Magnitude Trig 01 - DSO Width Trig Less Than 10 - DSO Width Trig Greater or Equal 11 - Not used

7 - not used

0x05 W

0,2 - TrigChSelVal

000 - ChA 001 - ChB 010 - Logic 011 - nc 100 - SPI 101 - I2C 110 - nc 111 - nc

3 - LogTrigSlp
4 - DC Relay Ch0, 0 = AC, 1 = DC
5 - DC Relay Ch1, 0 = AC, 1 = DC
6 - Attn Ch0, 0 = /10, 1 = /1
7 - Attn Ch1, 0 = /10, 1 = /1

0x06 W

0 - SCLK
1 - SDIO
2 - CSB (active H)
3 - CSDAC1 (active H)
4 - CSDAC2 (active H)
5 - CSMem (active H)
6,7 - Not Used

0x07 W

0..7 - TrigPos(0..7)

0x08 W

0..7 - TrigPos(8,15)

0x09 W

0,1 - Clk source select 00=50Mhz, 01=100Mhz, 10=200Mhz, 11= 20Mhz and below
2,7 - ClkDiv bit 8,13

0x0A W

0..7 -  ClkDiv bit 0..7 (Clk rate = 100 Mhz / (ClkDiv-1)

0x0B W

0..7 - TrigWidthVal(0..7)

0x0C W

0..7 - Logic Tirgger Val

0x0D W

0..7 - Logic don't Care, 1 marks the bit position of don't care bit	

0x0E W

0 - FSMReset 1= resets DSO FSM (pulse on write to reg) 	
1 - Armed DSO 1= Arms DSO for capture (pulse on write to reg)	
2 - ReadMode 1= Buffer Read Back, 0= DSO 	
3 - TrigEnd 1= Forces a fake trig (pulse on write to reg)	
4 - PwrDn 1= power down default = 0		
5 - not use
6 - ADCRst 1= Reset ADC default = 0 needs software pulse	
7 - not use

0x0F W

*0 - Alternate Address Page 1
*1 - Alternate Address Page 2
2 - not used
3 - not used
4 - TrigOutSel, 1 = Cal 1khz out 0 = TrigPulseOut, Default = Off
5 - SlwClkMode, 1 = On, 0 = Off, Default = Off
6 - Glitch Trigger, 1 = On, 0 = Off, Default = Off
7 - Auto Trigdone reply control, Default = off 

Serial Trigger Registers

*Alt_2 0x00 Serial TrigWd (31 downto 24) first bits to enter the shift register
*Alt_2 0x01 Serial TrigWd (23 downto 16)
*Alt_2 0x02 Serial TrigWd (15 downto 8)
*Alt_2 0x03 Serial TrigWd (7 downto 0) last bits to enter the shift register
*Alt_2 0x04 Serial TrigWd Ignor(31 downto 24)
*Alt_2 0x05 Serial TrigWd Ignor(23 downto 16)
*Alt_2 0x06 Serial TrigWd Ignor(15 downto 8)
*Alt_2 0x07 Serial TrigWd Ignor(7 downto 0)
*Alt_2 0x08 0,1 - SPI Mode
 00 - Mode 0
 01 - Mode 1
 10 - Mode 2
 11 - Mode 3
 2 -  SPI Trigdata Source, 0 = SI, 1 = SO, default = SI
 3..7 - Not used